In recent years, there is an ongoing reduction of frame width in display panels used for OA (Office Automation). More specifically, a frame member circumferentially encompassing a cabinet which holds a display panel body has an increasingly narrower width. Conventionally, signal wiring lines are provided in the frame member having a large width dimension. It is a recent trend to provide the signal wiring lines on the chip side of the display panel so that its frame width is reduced. The ongoing trend, however, structurally complicates a semiconductor integrated circuit configured to drive the display panel, making a test analysis difficult.
A conventional semiconductor integrated circuit configured to drive a display panel is described below. The semiconductor integrated circuit is capable of driving the display panel through dot inversion, wherein there are three gradation reference potential inputs for positive and negative polarities respectively, and the display gradation of a liquid crystal panel has 64 gradation levels, and number outputs for driving liquid crystal particles is 2 p (p is a positive integer number).
FIGS. 6 and 7 are circuit diagrams of a semiconductor integrated circuit configured to drive a display panel according to a prior art 1. The circuit elements illustrated in FIGS. 6 and 7 are described below. KH (1)-KH (64) are gradation wiring lines of positive polarity for supplying gradation potentials VH(1)-VH(64) in 64 gradation levels of positive polarity. KL (1)-KL (64) are gradation wiring lines of negative polarity for supplying gradation potentials VL (1)-VL (64) in 64 gradation levels of negative polarity. These two groups of gradation wiring lines having different polarities are separately arranged in juxtaposition.
GRH (a) is a resistance dividing circuit of positive polarity. The resistance dividing circuit of positive polarity GRH (a) includes a plurality of resistors serially connected to one another. These resistors are respectively provided between the wiring lines adjacent to each other in the 64 gradation wiring lines of positive polarity KH (1)-KH (64). The resistance dividing circuit of positive polarity GRH (a) thus configured generates the gradation potentials VH (1)-VH (64) in 64 gradation levels of positive polarity.
GRL (a) is a resistance dividing circuit of negative polarity. The resistance dividing circuit of negative polarity GRL (a) includes a plurality of resistors serially connected to one another. These resistors are respectively provided between the wiring lines adjacent to each other in the 64 gradation wiring lines of negative polarity KL (1)-KL (64). The resistance dividing circuit of negative polarity GRL (a) thus configured generates the gradation potentials VL (1)-VL (64) in 64 gradation levels of negative polarity.
SH (1)-SH (p) are p number of gradation selector circuits of positive polarity. The gradation selector circuits of positive polarity SH (1)-SH (p) are arranged in juxtaposition along a direction (lateral direction) X where the gradation wiring lines of positive polarity KH (1)-KH (64) are routed. The gradation selector circuits of positive polarity SH (1)-SH (p) are each configured to select one of the gradation potentials VH (1)-VH (64) in 64 gradation levels of positive polarity generated by the gradation wiring lines of positive polarity KH (1)-KH (64).
SL (1)-SL (p) are p number of gradation selector circuits of negative polarity. The gradation selector circuits of negative polarity SL (1)-SL (p) are arranged in juxtaposition along a direction (lateral direction) X where the gradation wiring lines of negative polarity KL (1)-KL (64) are routed. The gradation selector circuits of negative polarity SL (1)-SL (p) are each configured to select one of the gradation potentials VL (1)-VL (64) in 64 gradation levels of negative polarity generated by the gradation wiring lines of negative polarity KL (1)-KL (64).
The p number of gradation selector circuits of positive polarity SH (1)-SH (p) aligned along the lateral direction (gradation wiring routing direction) X are consolidated in one block, constituting a group of gradation selector circuits of positive polarity SHG. Similarly, the p number of gradation selector circuits of negative polarity SL (1)-SL (p) aligned along the lateral direction (gradation wiring routing direction) X are consolidated into a group of gradation selector circuits of negative polarity SLG. The group of gradation selector circuits of positive polarity SHG and the group of gradation selector circuits of negative polarity SLG are provided separately from each other in different regions along a direction where the gradation wiring lines are provided in juxtaposition (direction orthogonal to the gradation wiring routing direction: longitudinal direction).
VGH (1), VGH (2), and VGH (3) are electrode pads for applying a gradation reference potential of positive polarity. More specifically, VGH (1) is an electrode pad directly connected to the most significant gradation wiring line of positive polarity KH (1) in the 64 gradation wiring lines of positive polarity KH (1)-KH (64), VGH (3) is an electrode pad directly connected to the least significant gradation wiring line of positive polarity KH (64), and VGH (2) is an electrode pad directly connected to the intermediate gradation wiring line of positive polarity KH (32).
VGL (1), VGL (2), and VGL (3) are electrode pads for applying a gradation reference potential of negative polarity. More specifically, VGL (1) is an electrode pad directly connected to the most significant gradation wiring line of negative polarity KL (1) in the 64 gradation wiring lines of negative polarity KL (1)-KL (64), VGL (3) is an electrode pad directly connected to the least significant gradation wiring line of negative polarity KL (64), and VGL (2) is an electrode pad directly connected to the intermediate gradation wiring line of negative polarity KL (32).
BF (1)-BF (2p) are buffers each configured to select an output and apply low-impedance conversion to the selected output. The first buffer BF (1) and the second buffer BF (2) are paired with each other. The first buffer BF (1) arbitrarily selects one of outputs of the first gradation selector circuit of positive polarity SH (1) and the first gradation selector circuit of negative polarity SL (1) and applies the low-impedance conversion to the selected output, and then outputs the post-conversion output as a liquid crystal drive output OUT (1). The second buffer BF (2) selects the other one of the outputs of the first gradation selector circuit of positive polarity SH (1) and the first gradation selector circuit of negative polarity SL (1) and applies the low-impedance conversion to the selected output, and then outputs the post-conversion output as a liquid crystal drive output OUT (2).
The third buffer BF (3) and the fourth buffer BF (4) are paired with each other. The third buffer BF (3) arbitrarily selects one of outputs of the second gradation selector circuit of positive polarity SH (2) and the second gradation selector circuit of negative polarity SL (2) and applies the low-impedance conversion to the selected output, and then outputs the post-conversion output as a liquid crystal drive output OUT (3). The fourth buffer BF (4) selects the other one of the outputs of the second gradation selector circuit of positive polarity SH (2) and the second gradation selector circuit of negative polarity SL (2) and applies the low-impedance conversion to the selected output, and then outputs the post-conversion output as a liquid crystal drive output OUT (4).
Similarly, a (2p−1)th buffer BF (2p−1) and a (2p)th buffer BF (2p) are paired with each other. The (2p−1)th buffer BF (2p−1) arbitrarily selects one of outputs of a (p)th gradation selector circuit of positive polarity SH (p) and a (p)th gradation selector circuit of negative polarity SL (p) and applies the low-impedance conversion to the selected output, and then outputs the post-conversion output as a liquid crystal drive output OUT (2p−1). The (2p)th buffer BF (2p) selects the other one of the outputs of the (p)th gradation selector circuit of positive polarity SH (p) and the (p)th gradation selector circuit of negative polarity SL (p) and applies the low-impedance conversion to the selected output, and then outputs the post-conversion output as a liquid crystal drive output OUT (2p).
In the semiconductor integrated circuit thus configured, outputs of a gradation selector circuit of positive polarity SH (i) and a gradation selector circuit of negative polarity SL (i) are inputted to an arbitrary buffer BF (2i), wherein “I” is an arbitrary positive integer (i=1, 2 . . . , p). The gradation selector circuit of positive polarity SH (i) is in proximity to the buffer BF (2i), whereas the gradation selector circuit of negative polarity SL (i) is not in proximity to the buffer BF (2i). To minimize the wiring lines to be routed, therefore, it is desirable to arrange the group of gradation selector circuits of negative polarity SLG as close to the group of gradation selector circuits of positive polarity SHG as possible. This positional arrangement is similarly desirable independent of the polarity, positive or negative.
According to the prior art 1, all of the resistors in the resistance dividing circuit of positive polarity GRH (a) are arranged on the right side of the group of gradation selector circuits of positive polarity SHG facing the drawing, while all of the resistors in the resistance dividing circuit of negative polarity GRL (a) are arranged on the left side of the group of gradation selector circuits of negative polarity SLG facing the drawing. In the illustration of FIG. 6, the 64 gradation wiring lines of positive polarity KH (1)-KH (64) branch from the resistance dividing circuit of positive polarity GRH (a) on the upper side of the drawing and extend rightward and leftward, and the 64 gradation wiring lines of negative polarity KL (1)-KL (64) branch from the resistance dividing circuit of negative polarity GRL (a) on the lower side of the drawing and extend rightward and leftward. In the illustration of FIG. 7, the 64 gradation wiring lines of positive polarity KH (1)-KH (64) branch from the resistance dividing circuit of positive polarity GRH (a) on the right side of the drawing and extend leftward, and the 64 gradation wiring lines of negative polarity KL (1)-KL (64) branch from the resistance dividing circuit of negative polarity GRL (a) on the left side of the drawing and extend rightward.
A consideration is given to current leakage resulting from the occurrence of short circuit between the gradation wiring lines. The gradation wiring lines KH (1)-KL (64) are often very lengthy lines because they are routed in juxtaposition along a relatively long interval between the gradation selector circuit SH (1) and the gradation selector circuit SL (p). Therefore, there is the risk of short circuit between the gradation wiring lines due to any failure in a semiconductor manufacturing process.
FIGS. 8 and 9 illustrate a circuit condition after a short circuit occurred between the gradation wiring lines in the circuit diagrams of FIGS. 6 and 7. A reference numeral 30 indicates the short circuit generated between the gradation wiring lines. When a potential is applied to a terminal as illustrated in FIG. 8 to trace any short circuit between the gradation wiring lines, there is no current flow. When the potential is applied to two terminals as illustrated in FIG. 9, there is a constant current flow, which makes it difficult to determine whether the current results from the short circuit between the gradation wiring lines. When the current leakage is thus checked by simply applying the potential, it is difficult to decide whether the gradation wiring lines are short-circuited, leading to an increase of testing steps. Thus, it is inconvenient to test whether the gradation wiring lines are short-circuited in the prior art 1 illustrated in FIGS. 6 and 7.
FIG. 10 illustrates a circuit improved to more readily check whether the gradation wiring lines are short-circuited by any failure in a semiconductor manufacturing process. The circuit is called a prior art 2 and described below in detail. According to a characteristic of the prior art 2, the layout area of the 64 gradation wiring lines of positive polarity KH (1)-KH (64) and the resistance dividing circuit of positive polarity GRH (a) is enlarged downward facing the drawing, while the layout area of the 64 gradation wiring lines of negative polarity KL (1)-KL (64) and the resistance dividing circuit of negative polarity GRL (a) is enlarged upward facing the drawing. The respective layout areas are thus enlarged so that gradation wiring lines of positive polarity KH (j) extending from the right side facing the drawing toward the center and gradation wiring lines of negative polarity KL (j) extending from the left side facing the drawing toward the center are alternately provided in an indented manner (j=1, 2, . . . , 64). More specifically, the gradation wiring lines of positive polarity KH (j) and the gradation wiring lines of negative polarity KL (j) are alternately provided in the following order; KH (1), KL (1), KH (2), KL (2), KH (3), KL (3), . . . KH (32), KL (32), . . . , KH (64), KL (64).
According to another characteristic of the prior art 2, the layout area of the p number of gradation selector circuits of positive polarity SH (1)-SH (p) according to the prior art 1 is reduced in width but enlarged downward, while the layout area of the p number of gradation selector circuits of negative polarity SL (1)-SL (p) is reduced in width but enlarged upward. Two adjacent ones of the gradation selector circuits of positive polarity and two adjacent ones of the gradation selector circuits of negative polarity are alternately provided (there is one gradation selector circuit at both ends); SH (1), <SL (1), SL(2)>, <SH (2), SH (3)>, <SL (3), SL (4)>, <SH (4), SH (5)>, . . . , <SL (p−1), SL (p)>, SH(p).
The second prior art 2 is technically characterized in that one of the gradation wiring lines adjacent to each other in the gradation wiring juxtaposition direction Y is the gradation wiring line of positive polarity KH (j) extending from the resistance dividing circuit of positive polarity GRH (a) on the right side, while the other one of the gradation wiring lines adjacent to each other in the gradation wiring juxtaposition direction Y is the gradation wiring line of negative polarity KL (j) extending from the resistance dividing circuit of negative polarity GRL (a) on the left side (j=1, 2, . . . , 64). Thus, the gradation wiring lines of positive polarity and the gradation wiring lines of negative polarity are alternately provided.
Next is described a method of measuring a leak current generated between the gradation wiring lines of positive polarity KH (1)-KH (64) and the gradation wiring lines of negative polarity KL (1)-KL (64). A potential of positive polarity is applied to any of the electrode pads VGH (1)-VGH (3) to which the gradation reference potential of positive polarity is inputted, while a potential of negative polarity is applied is applied to any of the electrode pads VGL (1)-VGL (3) to which the gradation reference potential of negative polarity is inputted. If the adjacent ones of the gradation wiring lines of positive polarity KH (j) extending from the right side and the gradation wiring lines of negative polarity KL (j) or KL (j−1) extending from the left side are undergoing short circuit, the leak current flows between an electrode pad VGH (x) to which the gradation reference potential of positive polarity is applied and an electrode pad VGL (y) to which the gradation reference potential of negative polarity is applied. Then, it is known from the leak current flow that the short circuit is occurring between the gradation wiring lines (x=1, 2, 3, y=1, 2, 3).
The method of measuring the leak current described so far can easily check whether the gradation wiring lines are undergoing short circuit due to any failure in a semiconductor manufacturing process. As far as the gradation wiring lines adjacent to each other are in normal condition with no short circuit therebetween, there is no current flow therebetween because they are electrically insulated from each other. Thus, whether there is a leak current (whether the gradation wiring lines are short-circuited) is determined based on the recognition that an abnormal condition should be suspected in the event of any current flow that cannot occur in normal condition.